This invention relates to array processors.
An array processor is defined herein as a data processing system comprising a plurality of processing elements which are operable in parallel upon separate data streams under the control of a common stream of control signals. Thus, all the elements perform basically the same sequence of operations (subject to possible modifications by activity bits within the individual elements or by control signals which are specific to particular groups of elements), but on different data. With such a processor, as many operations can be performed simultaneously as there are elements, and hence the data throughput can be very high.
In such a processor, the processing elements may be connected together by data paths which permit neighbouring elements to transfer data. For example, in a two-dimensional rectangular array, each element may be connected to its four nearest neighbours in the north, east, south and west directions.
Because of its repetitive structure, an array processor is particularly suitable for implementation by integrated circuit techniques. In particular, each processing element may be formed as a separate large scale integrated circuit (LSI) chip or, preferably, a sub-array of processing elements may be formed as a single LSI chip.
In integrated circuit technology, while the cost per gate is low, the cost per pin is relatively high. Therefore, it is desirable to keep the number of connections to each chip as small as possible.
One object of the present invention is to reduce the number of pins required on each chip for the purpose of routing data between neighbouring processing elements.